There are many types of memory circuits, such as static read access memory (SRAM), dynamic read access memory (DRAM), electrically erasable read only memory (EEPROM), flash memory, and other types of memory circuits. These memory circuits typically comprise a plurality of memory cells organized in a two-dimensional array. The memory cells are accessed by way of parallel word lines extending along one dimension (e.g., along the rows) of the memory array, and bit lines extending along an orthogonal dimension (e.g., along the columns) of the memory array. A particular memory cell is typically accessed by activating or applying a particular voltage to a word line coupled to that cell, and sensing a response from or applying another particular voltage to a bit line coupled to that cell.
In particular, with regard to writing data to a memory cell of a memory array circuit, a write driver is typically employed for writing data to cells in a particular column. The write driver is coupled to the bit line and the complementary bit line pertaining to a column of cells. When a data value of one (1) is to be written to a particular cell belonging to a column of cells, the word line coupled to the cell is activated. This has the effect of coupling the corresponding bit line and corresponding complementary bit line to the cell. The write driver is also activated to generate a logic high signal on the corresponding bit line, and a logic low signal on the corresponding complementary bit line. If the cell previously stored a data value of zero (0), the cell would change state and store a data value of one (1) in response to the bit line and the complementary bit line being driven to logic high and logic low, respectively. If, on the other hand, the cell previously stored a data value of one (1), the state of the cell would remain unchanged. The writing of a data value of zero (0) operates in a similar manner, except that the write driver generates a logic low signal on the corresponding bit line, and a logic high signal on the corresponding complementary bit line.
Often, the memory array circuit is incorporated into an integrated circuit along with other types of circuitry that may need interface to (e.g., read data from or write data to) with the memory array circuit. Generally, the logic level voltages required by the write driver to write data to memory cells are typically higher than the logic level voltages used by other types of circuitry on the same integrated. Accordingly, the write driver should be configured to level shift the voltages used by the other circuitry from a lower voltage domain to a higher voltage domain suitable for writing data to the memory array circuit.
Additionally, the write driver should not interfere or minimally interfere with the corresponding bit line and complementary bit line when no data is being written to a cell in the associated column. For instance, when data is read from a cell through the use of a sense amplifier, the write driver should not affect the ability of the sense amplifier to sense the voltage or data value stored in the cell. Accordingly, the write driver should be configured to substantially not interfere with the corresponding bit line and complementary bit line during times when no data is being written to a memory cell.